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计算机工程 ›› 2006, Vol. 32 ›› Issue (14): 243-245. doi: 10.3969/j.issn.1000-3428.2006.14.089

• 工程应用技术与实现 • 上一篇    下一篇

一类复杂芯片的FPGA验证

李小波1,2;张 珩2;张福新2;唐志敏2   

  1. 1. 首都师范大学与中国科学院计算技术研究所计算机科学联合研究院,北京 100037;2. 中国科学院计算技术研究所,北京 100080
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2006-07-20 发布日期:2006-07-20

FPGA Verification for a Kind of Complicated Chip

LI Xiaobo1 ,2;ZHANG Heng2, ZHANG Fuxin2, TANG Zhimin2   

  1. 1. Joint School of Computer Science, Capital Normal University & Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100037; 2. Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080
  • Received:1900-01-01 Revised:1900-01-01 Online:2006-07-20 Published:2006-07-20

摘要: 介绍了模块层次构造算法和改进的K-L算法对设计进行划分,有效地减少了FPGA间的互连信号数。通过引脚复用(CPM)的方法,解决了多块FPGA间互连过多而引起的引脚不足问题。另一方面,FPGA的运行频率远远低于实际芯片的工作频率,通过在接口设置延迟寄存器和修改系统软件可以准确评估实际流片芯片的性能,实验的误差在2%以内。

关键词: FPGA验证, 模块划分, 引脚复用(CPM), 性能评估

Abstract: This paper introduces a module hierarchy construction algorithm and an improved K-L algorithm which efficiently reduce the number of the interconnect signals during the partition of the design. It employs the CPM (certify pin multiple) method to solve the insufficiency of pins caused by the too many interconnections between several FPGAs. On the other hand, the working frequency of FPGA is much lower than that of the actual chips, so it adds delay registers in the interface and modifies the system software to evaluate the actual performance of the taped out chips, and the experiment result shows that the error is below 2%.

Key words: FPAG verification, Modules partitioning, Certify pin multiple(CPM), Performance evaluating