摘要： 提出了一种面积优化的Reed-Solomon(RS)解码器实现方法，其运用折叠结构来实现解码过程矢量运算的求解电路。该方法提高了解码器主要运算部件的复用率，缩减了其电路规模。基于TSMC 0.25标准单元库的实现结果显示该文设计的解码器电路规模为约27 000门，与同类设计相比规模最大可缩减39%，该设计已集成在一款符合DVB-C标准的HDTV信道解调芯片中并已通过实场测试。
关键词:
RS解码器,
集成电路,
数字电视
Abstract: This paper presents a new area-efficient VLSI implementation method for Reed-Solomon (RS) decoder. By using the folding architecture to implement the equation solving circuits, this method can improve the reuse rate of main computation unit, simplify the hardware structure and reduce the chip area. Based on the TSMC 0.25 standard cell library, the proposed RS decoder consists of about 27 000 gates, which is about 39% smaller than the same kind of conventional ones. It has been integrated in a channel demodulation chip for HDTV and has been tested successfully in practice.
Key words:
Reed-solomon decoder,
VLSI,
HDTV
中图分类号:
郭艳飞;李占才;王 沁. HDTV中面积优化的RS解码器VLSI实现[J]. 计算机工程, 2006, 32(16): 11-13,2.
GUO Yanfei;;LI Zhancai; WANG Qin. An Area-efficient VLSI Design of Reed-Solomon Decoder for HDTV[J]. Computer Engineering, 2006, 32(16): 11-13,2.