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计算机工程 ›› 2006, Vol. 32 ›› Issue (18): 240-242. doi: 10.3969/j.issn.1000-3428.2006.18.086

• 工程应用技术与实现 • 上一篇    下一篇

基于WISHBONE的可兼容存储器控制器设计

陈双燕1,2,王东辉1,张铁军1,侯朝焕1   

  1. (1. 中国科学院声学研究所数字系统集成实验室,北京 100080;2. 中国科学院研究生院,北京 100080)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2006-09-20 发布日期:2006-09-20

Design of Compatible Memory Controller Based on WISHBONE Bus

CHEN Shuangyan1,2, WANG Donghui1, ZHANG Tiejun1, HOU Chaohuan1   

  1. (1. Lab of Mathematical Integration System, Institute of Acoustics, Chinese Academy of Sciences, Beijing 100080; 2. Graduate School of Chinese Academy of Sciences, Beijing 100080)
  • Received:1900-01-01 Revised:1900-01-01 Online:2006-09-20 Published:2006-09-20

摘要: 随着近年来高速计算机的快速发展,人们对存储器频宽及性能的要求越来越高。作为第2代DDR存储器的DDR2 SDRAM具有高速、低功耗、高密度、高稳定性等特点,在未来的一二年里,它将逐步取代DDR SDRAM而成为内存的主流。尽管DDR2的地位正在不断上升,但DDR仍是当前流行的高速存储器。该文通过对这两种存储器的分析比较,基于WISHBONE总线,提出并实现了一种可兼容DDR与 DDR2存储器的控制器。

关键词: DDR SDRAM, DDR2 SDRAM, WISHBONE, 控制器

Abstract: With the rapid increases of computer performance in recent years, designers face great challenges such as increasing the frequency and increasing the performance of memory. Compared with the DDR SDRAM, DDR2 SDRAM has higher speed, lower power, higher efficiency and higher stability. A recent statistics shows that DDR2 will become popular in one or two years, but DDR still prevails today. For this reason, this article deals with the design and implementation of the DDR/DDR2 SDRAM compatible controller based on a common standard bus interface.

Key words: DDR SDRAM, DDR2 SDRAM, WISHBONE, Controller