摘要： 研究了5Gbps~40Gbps交换技术和IP软核的实现方法。采用多层结构、模块化的设计思想，使用Verilog硬件描述语言对40Gbps宽带交换电路进行编程，实现了一种通用的、容量可变的、可移植的宽带交换电路的IP软核，可以将其应用到SDH设备中的数字交叉连接电路中。
关键词:
IP软核,
同步数字系列,
T-S-T交换,
功能验证
Abstract: This paper researches the implementation methods of the 5Gbps~40Gbps switch technology and IP soft-core. With the design idea of multilayer and modularization, it programs the 40Gbps broad band switch circuit in Verilog HDL. It realizes a versatile, alterable capability, transplantable IP Soft-core of the broad band switch circuit. The IP core can be used in the DXC circuits of the SDH equipment.
Key words:
IP soft-core,
Synchronous digital hierarchy(SDH),
T-S-T switch,
Function verification
李宥谋;蒋 林;韩俊刚. 5Gbps~40Gbps宽带交换软核的设计与实现[J]. 计算机工程, 2007, 33(04): 230-232.
LI Youmou; JIANG Lin; HAN Jungang. Design and Implementation of 5Gbps ~40Gbps Broad Band Switch Soft-core[J]. Computer Engineering, 2007, 33(04): 230-232.