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计算机工程 ›› 2007, Vol. 33 ›› Issue (04): 239-240. doi: 10.3969/j.issn.1000-3428.2007.04.084

• 工程应用技术与实现 • 上一篇    下一篇

提高硬件多线程处理器性能的方法

王传福,周学海   

  1. (中国科学技术大学计算机科学与技术系,合肥 230026)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2007-02-20 发布日期:2007-02-20

Method to Enhance Performance of Hardware
Multithread Processor

WANG Chuanfu, ZHOU Xuehai   

  1. (Department of Computer Science and Technology, University of Science and Technology of China, Hefei 230026)
  • Received:1900-01-01 Revised:1900-01-01 Online:2007-02-20 Published:2007-02-20

摘要: 在当今的网络处理器中,为了提高吞吐率、实现高性能,部分处理器采用了流水线技术和硬件多线程技术。支持硬件多线程不仅有效地隐藏了访存延迟,而且略去了线程切换时线程相关信息的保存与恢复,减少了线程切换的开销,从而提高了性能。然而硬件多线程并未能彻底消除线程切换的开销,线程切换时仍需要清除与重载流水线,这将浪费一定的时钟周期,不能充分利用多线程带来的好处。该文在IXP2400网络处理器的基础上,提出了一种新的设计方法,使得线程切换时略去了清除与重载流水线的环节,减少了这部分的开销,从而提高了处理器性能。

关键词: 网络处理器, 硬件多线程, 零延迟切换

Abstract: In order to enhance the turnover rate and the performance, some NPUs have used the pipeline technology and the hardware multithread technology. Hardware multithreading can effectively hide the delay of accessing memory, and reduce the expenses of thread changing, thus enhance the performance. But the hardware multithread can’t fully eliminate the expenses of thread changing, it still needs to flush and reload the pipeline, this would waste some clock cycles, could not fully take the advantage of using multithread. This paper proposes one new design method, which can reduce this part of expenses, then enhance the performance of processors.

Key words: NPU, Hardware multithread, Zero delay switch