计算机工程 ›› 2007, Vol. 33 ›› Issue (21): 237-239.doi: 10.3969/j.issn.1000-3428.2007.21.084

• 工程应用技术与实现 • 上一篇    下一篇

VelociTI结构浮点DSPs寄存器堆读写的流水线设计

胡正伟1,2,仲顺安1,陈 禾1   

  1. (1. 北京理工大学电子工程系,北京 100081;2. 华北电力大学电子与通信工程系,保定 071003)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2007-11-05 发布日期:2007-11-05

Pipeline Design for Reading and Writing of Register File of DSPs
Based on VelociTI Architecture

HU Zheng-wei1,2, ZHONG Shun-an1, CHEN He1   

  1. (1. Departerment of Electronic Engineering, Beijing Institute of Technology, Beijing 100081;
    2. Departerment of Electronic and Communication Engineering, North China Electric Power University, Baoding 071003)
  • Received:1900-01-01 Revised:1900-01-01 Online:2007-11-05 Published:2007-11-05

摘要: 研究了VelociTI结构浮点数字信号处理器寄存器堆的流水线读写原理并提出了一种设计方法。该方法对单操作数双精度浮点指令采用2个32位数据通路用1个流水线周期读取源操作数,双操作数双精度浮点指令采用锁定译码单元,利用若干流水线周期读取源操作数。采用写控制向量的方法实现了流水线多个周期执行写操作。该方法正确实现了基于IEEE754标准的双精度浮点数据在寄存器堆与功能单元之间的32位数据通路上的传输,仿真结果验证了其正确性。

关键词: VelociTI结构, 流水线, 寄存器堆, 浮点数据

Abstract: Principle of reading and writing of register file of digital signal processor based on VelociTI architecture is studied and one design method is proposed. Reading of single operand double precision floating point instructions is accomplished by using two 32 bits data path in one pipeline cycle. For two-operand double precision floating point instructions, decode unit is locked until all operands are accessed. Writing control signal vector is adopted for writing. Double precision floating point data based on IEEE754 standard can be accessed with 32 bits data path by using this method. The correctness is conformed by simulation results.

Key words: VelociTI architecture, pipeline, register file, floating point data

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