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计算机工程 ›› 2007, Vol. 33 ›› Issue (23): 228-229,. doi: 10.3969/j.issn.1000-3428.2007.23.080

• 工程应用技术与实现 • 上一篇    下一篇

一种精简的二维DWT结构设计

曹志研,季振洲,胡铭曾   

  1. (哈尔滨工业大学计算机科学与技术学院,哈尔滨 150001)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2007-12-05 发布日期:2007-12-05

Reduced Architecture Design of 2D DWT

CAO Zhi-yan, JI Zhen-zhou, HU Ming-zeng   

  1. (School of Computer Science and Technology, Harbin Institute of Technology, Harbin 150001)
  • Received:1900-01-01 Revised:1900-01-01 Online:2007-12-05 Published:2007-12-05

摘要: 设计了一种低功耗的二维离散小波变换(DWT)结构,用于无线传感器网络中的图像压缩。该结构实现了精简复杂性的(5,3)整数离散小波变换,采用流水线和延迟线技术,在获得高运算吞吐率的同时,使数据尽可能被处理单元高效利用,以减少对片内存储器和片外存储器的访问次数。多级二维DWT采用展开方法实现,这种方法可尽早开始下一级变换,不需要大的片内存储器和片内存取操作。模拟试验和FPGA实现验证了系统在满足需要性能的前提下具有低复杂性、低功耗、片内存储器小等优点。

关键词: 离散小波变换, 图像压缩, FPGA

Abstract: This paper designs a low-power-consumption architecture of 2-D discrete wavelet transform (DWT) for image compression in the wireless sensor network. The architecture implements reduced complexity algorithm of DWT-(5, 3) integer DWT. It adopts pipeline and delay-line design technology to get high computation throughput and make data used by processing unit efficiently, reducing the number of on-chip and off-chip memory access. Multi-level DWT is implemented by unwinding, which makes the next level transforming start as early as it can without large in-chip memory and access operations. Simulation and FPGA implementation show the system satisfies the required performance, and it has the merits such as low complexity, low power consumption, small in-chip memory etc.

Key words: discrete wavelet transform (DWT), image compression, FPGA

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