摘要：

冗余符号数加法器满足了对加法器高速度和高精度的要求。该文针对二进制符号数加法传统算法的不足，提出了一种改进算法，设计了相应的加法电路。它采用3级结构实现加法器，结构简单而规则，中间进位与中间和都仅需要1bit编码。与传统结构相比，该算法实现的电路速度更快、面积更小、动态功耗更少。

关键词: 二进制符号数, 快速加法器, 4-2加法器, 计算机算法

Abstract: Because of the requirements for high speed and high precision in adders, redundant signed digit number adders are proposed. On account of weaknesses of traditional signed binary addition, this paper proposes an improved arithmetic and designs the addition circuit. It is with a simple and regular 3-stage structure, and its immediate carry and sum digits are both encoded with 1bit. Contrast to the traditional one, the improved circuit has higher speed and consumes less area and dynamic power.

Key words: binary signed digit number, fast adder, four-to-two adder, computer arithmetic

中图分类号: 

• TN402