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计算机工程 ›› 2008, Vol. 34 ›› Issue (17): 229-231. doi: 10.3969/j.issn.1000-3428.2008.17.082

• 工程应用技术与实现 • 上一篇    下一篇

基于跳跃式Wallace树的低功耗32位乘法器

李 伟,戴紫彬,陈 韬   

  1. (解放军信息工程大学电子技术学院,郑州 450004)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2008-09-05 发布日期:2008-09-05

Low-power 32-bit Multiplier Based on Leapfrog Wallace Tree

LI Wei, DAI Zi-bin, CHEN Tao   

  1. (Institute of Electronic Technology, PLA Information Engineering University, Zhengzhou 450004)
  • Received:1900-01-01 Revised:1900-01-01 Online:2008-09-05 Published:2008-09-05

摘要: 为了提高乘法器的综合性能,从3个方面对乘法器进行了优化设计。采用改进的Booth算法生成各个部分积,利用跳跃式Wallace树结构进行部分积压缩,通过改进的LING加法器对压缩结果进行求和。在FPGA上进行验证与测试,并在0.18 μm SMIC工艺下进行逻辑综合及布局布线。结果表明,与采用传统Wallace树结构的乘法器相比,该乘法器的延时减少了29%,面积减少了17%,功耗降低了38%,能够满足高性能的处理要求。

关键词: Booth算法, 跳跃式Wallace树, 乘法器, LING加法器

Abstract: In order to improve performance of multiplier, this paper adopts modified Booth algorithm to generate partial product, proposes the leapfrog Wallace tree architecture to compress partial product, and introduces the modified LING adder to compute the final sum of the result of Wallace tree. The design is realized by using Altera’s FPGA. Synthesis, placement and routing of 32-bit multiplier are accomplished on 0.18 μm SMIC process. Compared with conventional multiplier with traditional Wallace tree, the multiplier reduces the multiplication time, the power dissipation and the area of multiplier by 29%, 38% and 17%.

Key words: Booth algorithm, leapfrog Wallace tree, multiplier, LING adder

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