摘要： 提出一种针对H.264标准的CABAC解码器的硬件加速器的设计方案。通过采用高效的状态机和良好的SRAM组织结构，使平均解码速率达每周期1 bit，可以解码基于高档次的H.264码流，实现对高清码流(1 920×1 088)的实时解码，在中芯国际0.18 μm工艺标准单元库的基础上进行综合，面积占47 444门，工作时钟频率达196 MHz。
关键词:
H.264标准,
CABAC解码器,
高档次,
硬件加速器
Abstract: This paper proposes a design scheme of hardware accelerator for CABAC decoder in H.264. It develops an efficient FSM and SRAM system so that the decoder can generate 1 bit every cycle, and it is capable of decoding High Profile(HP) video stream, achieving the requirement of real-time decoding. An ASIC implementation of the design is carried out in a 0.18 µm standard cell library of silicon technology, the estimated frequency is 196 MHz and the area includes 47 444 gates.
Key words:
H.264,
CABAC decoder,
High Profile(HP),
hardware accelerator
中图分类号:
盛怀亮;林 涛. 全高清CABAC解码器的设计与实现[J]. 计算机工程, 2008, 34(19): 236-238,.
SHENG Huai-liang; LIN Tao. Design and Implementation of Full High Definition CABAC Decoder[J]. Computer Engineering, 2008, 34(19): 236-238,.