摘要： 针对如何使用硬件实现三角形光栅化，提高三角形光栅化速度，提出一种集裁减与填充于一体的三角形光栅化算法。在算法中扫描与采样算法相互独立，可以根据不同应用替换相应的采样算法。使用基于Xilinx Virtex 2P XC2VP30的FPGA平台的硬件方法实现了该算法。实验结果表明，在FPGA板上实际运行时，约2 500 ns就可以光栅化一个边长为5像素的等边三角形。

关键词: 光栅化, 图形学, FPGA板

Abstract: Based on how to realize triangle rasterization, and enhance the speed of triangle rasterization, a triangle raster algorithm which integrates clipping and filling is presented. The scan and sample algorithm is independent in this algorithm. The different sample algorithms can be used in different applications. The algorithm is realized on Xilinx Virtex 2P XC2VP30 FPGA. The experimental results show that the implementation can raster a triangle (an equilateral triangle which edges 5 pixels) in about 2 500 ns.

Key words: raster, graphics, FPGA

中图分类号: 

• TP391.41