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计算机工程 ›› 2009, Vol. 35 ›› Issue (1): 224-225,. doi: 10.3969/j.issn.1000-3428.2009.01.077

• 工程应用技术与实现 • 上一篇    下一篇

SoC测试中IP核透明路径的构建

王 飞1,谭 明2,何道君2,徐金甫1   

  1. (1. 解放军信息工程大学电子技术学院,郑州 450004;2. 总参谋部第五十一研究所,北京 100072)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-01-05 发布日期:2009-01-05

Construction of Transparent Paths for IP Cores in SoC Test

WANG Fei1, TAN Ming2, HE Dao-jun2, XU Jin-fu1   

  1. (1. Institute of Electronic Technology, PLA Information Engineering University, Zhengzhou 450004; 2. The Fifty-first Graduate School of General Staff, Beijing 100072)
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-01-05 Published:2009-01-05

摘要: 大量IP核复用于SoC中,给IP核的测试复用带来困难。该文给出一种基于透明路径的测试访问机制构建方法,对PARWAN处理器构建透明路径。实验结果表明,增加透明路径后的PARWAN处理器只增加少量占用的资源。将构建了透明路径的PARWAN处理器作为测试访问机制应用于SoC中,对其他IP核进行测试,能减少测试向量施加时间。

关键词: 测试访问机制, 透明路径, 扇出分支

Abstract: The reuse of IP cores in SoC brings more difficulties in the test reuse of IP core. This paper proposes a method of constructing Test Access Mechanism(TAM) based transparent paths. Experiment is performed on PARWAN processor. Experimental results show that PARWAN after constructing transparent paths has lower area overhead, and test application time reduces obviously when PARWAN constructed transparent paths is applied in SoC as TAM.

Key words: Test Access Mechanism(TAM), transparent path, fanout branches

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