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计算机工程 ›› 2009, Vol. 35 ›› Issue (11): 256-259. doi: 10.3969/j.issn.1000-3428.2009.11.089

• 工程应用技术与实现 • 上一篇    下一篇

DTMB系统全模式信道估计及硬件实现

潘 安,陈 赟,陈 媛,巫建明,曾晓洋   

  1. (复旦大学专用集成电路与系统国家重点实验室,上海 201203)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-06-05 发布日期:2009-06-05

Full-mode Channel Estimation and Hardware Implementation for DTMB System

PAN An, CHEN Yun, CHEN Yuan, WU Jian-ming, ZENG Xiao-yang   

  1. (State Key Lab of ASIC and System, Fudan University, Shanghai 201203)
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-06-05 Published:2009-06-05

摘要: 提出一种应用于全模式DTMB解调器的信道估计及均衡实现方案。该方案利用DTMB系统帧结构中的PN序列,可以同时支持 3种帧头模式及单多载波2种传输模式的信道估计及均衡。为易于硬件实现,对迭代干扰消除进行简化处理,并对信道均衡及信道冲击响应的滤波进行优化。给出一种硬件实现架构,兼顾性能和复杂度。仿真结果表明,简化后的算法几乎没有造成性能损失。

关键词: DTMB系统, PN序列, 信道估计, 全模式, 硬件架构

Abstract: This paper developes a full-mode channel estima¬tion for DTMB demodulator. The method utilizes the quasi-cyclic structure of PN sequence guard interval in DTMB system to obtain channel estima¬tion and equalization both in three kinds of frame head mode as well as in single and multi-carrier modulation transmission mode. To implement on hardware, interference cancellation is predigested, equalization and filter for channel impulse response are optimized. The VLSI architecture for channel estimation and equalization is proposed which works effectually and achieves low complexity as well. Computational simulation results show that the proposed scheme has little BER loss in performance.

Key words: DTMB system, PN sequence, channel estimation, full-mode, hardware architecture

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