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计算机工程 ›› 2009, Vol. 35 ›› Issue (20): 219-221. doi: 10.3969/j.issn.1000-3428.2009.20.078

• 工程应用技术与实现 • 上一篇    下一篇

基于FSL总线的JPEG解码协处理器

李庆诚1,白振轩1,2,刘 洋1,胡海军1   

  1. (1. 南开大学信息技术科学学院,天津 300071;2. 解放军后勤工程学院,重庆400016)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-10-20 发布日期:2009-10-20

JPEG Decoding Coprocessor Based on FSL Bus

LI Qing-cheng1, BAI Zhen-xuan1,2, LIU Yang1, HU Hai-jun1   

  1. (1. College of Information Technical Science, Nankai University, Tianjin 300071;2. Logistical Engineering University of PLA, Chongqing 400016)
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-10-20 Published:2009-10-20

摘要: 介绍一种面向嵌入式应用,能与Micrblaze处理器较好地异步协同工作,不需要专用双口RAM的JPEG解码协处理器。该JPEG解码器采用Verilog语言实现,能很好地处理JFIF格式的JPEG压缩文件,并且在只有少量缓冲空间的FIFO上能正确工作。验证实验结果表明,该处理器在xilinx公司的XUP Virtex II Pro开发板上,采用FSL总线与Microblaze 处理器相连,工作效率较高。

关键词: FSL总线, JPEG 解码器, 协处理器, 异步FIFO

Abstract: This paper introduces an embedded system oriented JPEG decoding coprocessor, which doesn’t need dual-port RAM and works well with Microblaze asynchronously. This decoder can decode JPEG file whose format is JFIF perfectly with few FIFO memory space by verilog. Certified in xilinx’s XUP Virtex II Pro development board, it works well through connection with Microblaze by FSL bus.

Key words: FSL bus, JPEG decoder, coprocessor, asynchronously FIFO

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