计算机工程 ›› 2010, Vol. 36 ›› Issue (3): 249-250,.doi: 10.3969/j.issn.1000-3428.2010.03.084

• 工程应用技术与实现 • 上一篇    下一篇

改进的仲裁器PUF设计与分析

张俊钦1,谷大武1,侯方勇2   

  1. (1. 上海交通大学计算机科学与工程系,上海 200240;2. 国防科学技术大学计算机学院,长沙 410073)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2010-02-05 发布日期:2010-02-05

Design and Analysis of Improved Arbiter PUF

ZHANG Jun-qin1, GU Da-wu1, HOU Fang-yong2   

  1. (1. Department of Computer Science and Engineering, Shanghai Jiaotong University, Shanghai 200240; 2. School of Computer, National University of Defense Technology, Changsha 410073)
  • Received:1900-01-01 Revised:1900-01-01 Online:2010-02-05 Published:2010-02-05

摘要: 介绍Daihyun等设计的仲裁器物理不可克隆函数(PUF)方案,指出其不足之处。在此基础上提出一种改进方案,设计并分析基于 D触发器的仲裁器PUF,在FPGA平台上实现并测试该方案的性能。实验结果表明,改进方案在输出的0, 1平衡性方面优于Daihyun的PUF方案。

关键词: 仲裁器物理不可克隆函数, 现场可编程逻辑阵列, D触发器

Abstract: This paper introduces the arbiter Physical Uncloneable Function(PUF) scheme designed by Daihyun, and gives its disadvantage. It presents an improved scheme, designs and analyzes the arbiter PUF based on D trigger. It implements the design on Field Programmable Gate Array(FPGA) platform and conducts experiments to evaluate the performance. Experimental results show that the improved method is better than the method designed by Daihyun in 0, 1 balance of output.

Key words: arbiter Physical Uncloneable Function(PUF), Field Programmable Gate Array(FPGA), D trigger

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