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计算机工程 ›› 2010, Vol. 36 ›› Issue (06): 241-243.doi: 10.3969/j.issn.1000-3428.2010.06.082

• 工程应用技术与实现 • 上一篇    下一篇

面向专用指令集处理器设计的软硬件协同验证

严迎建，杨志峰，任　方   

  1. (解放军信息工程大学电子技术学院，郑州 450004)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2010-03-20 发布日期:2010-03-20

Software-Hardware Co-verification for ASIP Design

YAN Ying-jian, YANG Zhi-feng, REN Fang   

  1. (Institute of Electronic Technology, PLA Information Engineering University, Zhengzhou 450004)
  • Received:1900-01-01 Revised:1900-01-01 Online:2010-03-20 Published:2010-03-20

PDF

1031

被引次数

9

摘要： 为提高专用指令集处理器设计中的验证效率和覆盖率，将专用指令集处理器的寄存器传输级设计验证与汇编器、指令集模拟器等软件开发工具的测试相结合，提出一种软硬件协同验证方法。该方法按照覆盖率要求由软件自动产生测试程序和数据，将利用汇编器产生的机器指令输入到指令集模拟器和硬件仿真工具分别进行软硬件仿真，通过软硬件仿真结果自动比对得出联合验证结果。实践证明，该方法能够有效提高验证效率和覆盖率，缩短验证周期。

关键词: 专用指令集处理器, 硬件仿真, 指令集模拟器, 软硬件协同验证

Abstract: To increase the efficiency of verification in design of Application Specific Instruction Set Processor(ASIP), a software-hardware co-verification method which combines the verification of ASIP Register Transport Level(RTL) description with the test of ASIP software development tools(assembler, software simulator) is proposed. Test assemble instructions and data are generated according to the test requirement, and the binary codes are produced by the assembler subsequently. The binary codes are input to the hardware simulator and instruction set simulator at same time, and the results of software and hardware simulation are compared automatically. This method can discover errors in ASIP RTL description, the assembler and the instruction set simulator efficiently, increase the coverage of verification, and shorten the verification cycle of ASIP.

Key words: Application Specific Instruction Set Processor(ASIP), hardware simulation, Instruction Set Simulator(ISS), software-hardware co-verification

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