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计算机工程 ›› 2010, Vol. 36 ›› Issue (11): 215-216,220. doi: 10.3969/j.issn.1000-3428.2010.11.078

• 工程应用技术与实现 • 上一篇    下一篇

基于分层结构的硬件仿真器设计

陆俊峰,洪 一,黄光红   

  1. (中国电子科技集团公司第38研究所集成电路设计中心,合肥 230031)
  • 出版日期:2010-06-05 发布日期:2010-06-05
  • 作者简介:陆俊峰(1978-),男,工程师、博士,主研方向:高性能嵌入式处理器体系结构设计,ASIC芯片设计;洪 一,研究员;黄光红,助理工程师

Design of Hardware Emulator Based on Hierarchy Structure

LU Jun-feng, HONG Yi, HUANG Guang-hong   

  1. (IC Design Center, No.38 Institute, China Electronics Technology Group Corporation, Hefei 230031)
  • Online:2010-06-05 Published:2010-06-05

摘要: 基于JTAG调试系统的硬件仿真器结构特点,提出分层结构的设计方法,将硬件仿真器划分为协议层和物理层。协议层负责将软件调试操作命令解析成一组基本的硬件微操作,物理层负责将硬件微操作的数据按照JTAG信号定义进行编码和解码操作。分层设计可以使各层根据自己的特点进行独立设计与优化,便于团队进行协作开发从而提高设计效率。

关键词: JTAG接口, 硬件仿真器, 分层设计方法

Abstract: Based on the features of JTAG debug system architecture, this paper proposes a hierarchy design method in which the emulator is classified into protocol and physical layer. In protocol layer, the emulator translates a debug operation into a set of hardware micro-operations. In physical layer, the emulator codes the data of micro-operations or decodes the signals received from target chip based on the JTAG specification. By this method, the different designer can focus on the characteristic of proper layer so that a few of different designers can cooperate on the emulator designing efficiently.

Key words: JTAG interface, hardware emulator, hierarchy design method

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