计算机工程 ›› 2011, Vol. 37 ›› Issue (01): 235-237.doi: 10.3969/j.issn.1000-3428.2011.01.081

• 工程应用技术与实现 • 上一篇    下一篇

QC-LDPC码的高性能译码器实现

田 雨,马林华,林志国   

  1. (空军工程大学工程学院航空电子工程系,西安 710038)
  • 出版日期:2011-01-05 发布日期:2010-12-31
  • 作者简介:Quasi-Cyclic LDPC(QC-LDPC) code; layered decoding algorithm; multi-rate; power-efficient

Implementation of QC-LDPC Code Decoder with High Performance

TIAN Yu, MA Lin-hua, LIN Zhi-guo   

  1. (Aeronautical Electronics Engineering Dept., Institute of Engineering, Air Force Engineering University, Xi’an 710038, China)
  • Online:2011-01-05 Published:2010-12-31

摘要: 在对分层译码算法优化的基础上,提出一种多码率QC-LDPC译码器。采用改进的分层消息传播算法实现快速收敛,将译码迭代次数降到经典方法的50%以下。架构中用于存储中间置信信息的存储器数量只有4个,减少了芯片面积和功耗。校验节点置信度更新采用校正的整数量化的分层算法,降低了计算复杂度。选取的校正因子降低了译码器的误码率。基于该架构实现QC-LDPC译码器,融合3种码率,芯片规模为60万门,时钟频率为110 MHz,1/2码率的译码速率可达134 Mb/s。

关键词: 准循环LDPC码, 分层译码算法, 多码率, 低功耗

Abstract: A multi-rate decoder of Quasi-Cyclic LDPC(QC-LDPC) decoder is presented based on the improvement of layered decoding algorithm. The implementation has larger bit throughput resulting from fast convergence speed by more than 50 percent in terms of decoding iterations. Only four memories are used to store the messages which significantly reduce the area and the power dissipation. Adjusted integer quantization of layered decoding algorithm for check-node updating reduces the complexity and the correction factor guarantees the error rate performance. The proposed decoding architecture is implemented in the standard recommended. The decoder consumes 0.6 million gates, and reaches a throughput of 134 Mb/s at a clock frequency of 110 MHz with rate of 1/2.

Key words: Quasi-Cyclic LDPC(QC-LDPC) code, layered decoding algorithm, multi-rate, power-efficient

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