摘要：

在基于低层虚拟机的四层C-to-VHDL可重构编译架构上，针对RAM访问和设计执行性能之间的矛盾，提出一种RAM读取优化算法。通过对IR访存指令及数据相关性的分析，创建专用数据通路，优化RAM的访存过程。实验结果表明，该优化算法能够有效减少RAM访问次数。

关键词: C-to-VHDL可重构编译, FPGA设计, 低层虚拟机, RAM访问优化

Abstract:

Aiming at the conflict between the RAM access and the design performance, in the four layer C-to-VHDL reconfigurable compiling framework which is based on Low Level Virtual Machine(LLVM) framework, this paper proposes an optimization algorithm for RAM access. By analyzing the load and store instruction in LLVM’s IR and the data dependence, it creats a dedicated data path to optimize the process of reading and writing to RAM. Experimental results show that the optimized algorithm can effectively reduce the access number to RAM.

Key words: C-to-VHDL reconfigurable compiling, FPGA design, Low Level Virtual Machine(LLVM), RAM access optimization

中图分类号: 

• TP391