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计算机工程 ›› 2011, Vol. 37 ›› Issue (4): 252-254. doi: 10.3969/j.issn.1000-3428.2011.04.091

• 工程应用技术与实现 • 上一篇    下一篇

ARM微处理器中断响应时间的实验研究

尹旭峰,苑士华,胡纪滨   

  1. (北京理工大学机械与车辆学院,北京 100081)
  • 出版日期:2011-02-20 发布日期:2011-02-17
  • 作者简介:尹旭峰(1972-),男,讲师、博士,主研方向:车辆电子,嵌入式系统,无线传感器网络;苑士华,教授、博士、博士生导师;胡纪滨,副教授、博士

Experimental Research on Interrupt Latency Time of ARM Microprocessor

YIN Xu-feng, YUAN Shi-hua, HU Ji-bin   

  1. (School of Mechanical Engineering, Beijing Institute of Technology, Beijing 100081, China)
  • Online:2011-02-20 Published:2011-02-17

摘要:

介绍ARM微处理器S3C2440A的中断处理机制,设计一种实验测定中断响应时间的方法,实测了理想状态下S3C2440A的快速中断FIQ和标准中断IRQ的响应时间,并对实验数据进行分析处理,给出实测数据的拟合函数,从而得出以下结论:FIQ与IRQ的中断响应时间基本相等,中断响应时间与CPU的运行时钟无关,只与中断控制器的运行时钟频率呈反比关系,启用高速缓存时的中断响应时间不到禁用高速缓存时的1/3。

关键词: 中断, 响应, 微处理器, 精简指令集计算机

Abstract:

The interrupt processing of ARM microprocessor S3C2440A is introduced briefly. An experiment to measure the interrupt latency time of FIQ and IRQ is designed and accomplished. Two fitting functions of the experimental data are given. It can be concluded that the interrupt latency time of FIQ and IRQ is almost the same. They have little relationship with the processor cycles and are only in inverse proportion to the frequency of the clock of the interrupt controller. The interrupt latency time while the cache is enabled is less than 1/3 of that while the cache is disabled.

Key words: interrupt, latency, microprocessor, Reduced Instruction Set Computer(RISC)

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