摘要： 基于现场可编程门阵列(FPGA)平台，设计嵌入式精简指令集计算机(RISC)中央处理器(CPU)。参考无内部互锁流水级微处理器(MIPS)指令集制定原则设计CPU指令集，通过分析指令处理过程构建嵌入式CPU的5级流水线，结合数据前推技术和软件编译方法解决流水线相关性问题，并实现CPU的算术逻辑单元、控制单元、指令cache等关键模块设计。验证结果表明，该嵌入式RISC CPU的速度和稳定性均达到设计要求。

关键词: 现场可编程门阵列, 精简指令集计算机处理器, 流水线相关性, 算术逻辑单元

Abstract: This paper designs a embedded Reduced Instruction Set Computer(RISC) Central Processing Unit(CPU) based on Field Programmable Gate Array(FPGA) platform. The instruction set is designed refer to Microprocessor without Interlocked Pipeline Stage(MIPS) instruction set principle. By analyzing the process of each instruction, the 5-stage pipeline of embedded CPU is built. It adopts data forwarding technology and software compiler method to solve pipeline-related problem. The key modules of CPU: Arithmetic Logic Unit(ALU), control unit, instruction cache are designed. Verification results show that the embedded RISC CPU speed and stability meet the design requirements.

Key words: Field Programmable Gate Array(FPGA), Reduced Instruction Set Computer(RISC) processor, pipelining correlation, Arithmetic Logic Unit(ALU)

中图分类号: 

• TP332.3