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计算机工程 ›› 2011, Vol. 37 ›› Issue (21): 238-240,251. doi: 10.3969/j.issn.1000-3428.2011.21.081

• 工程应用技术与实现 • 上一篇    下一篇

芯片级BIST控制器的设计与实现

孟 觉,樊晓光,邬 蒙,夏海宝   

  1. (空军工程大学工程学院,西安 710038)
  • 收稿日期:2011-04-22 出版日期:2011-11-05 发布日期:2011-11-05
  • 作者简介:孟 觉(1987-),男,硕士研究生,主研方向:机载计算机技术,综合模块化航空电子系统;樊晓光,教授、博士;邬 蒙,讲师、硕士;夏海宝,副教授、硕士
  • 基金资助:
    国家部委基金资助项目;航空科学基金资助项目

Design and Implementation of Chip-level BIST Controller

MENG Jue, FAN Xiao-guang, WU Meng, XIA Hai-bao   

  1. (College of Engineering, Air Force Engineering University, Xi’an 710038, China)
  • Received:2011-04-22 Online:2011-11-05 Published:2011-11-05

摘要: 为适应某型国产航电设备故障的实时自检测及定位需要,设计一个针对自测试电路的芯片级BIST控制器。传统的测试方法存在测试时间长和故障覆盖率不高的缺点。为此,采用伪随机测试向量和确定性测试向量相结合的混合BIST技术及多扫描链、压缩向量技术,对芯片级BIST控制器进行研究,给出功能模块的设计方案。利用Quartus II软件对设计进行仿真,测试结果证实该设计可达到某型航电设备的故障自检测要求。

关键词: 控制器, 内建自测试, 芯片级, 多扫描链, 压缩向量

Abstract: In order to meet the needs of real-time and self-test of some domestic avionic equipment malfunction, the chip-level Build-in-Self-Test (BIST) controller aiming at self-test circuit is designed. The traditional test method has defects of time-consuming process and low fault coverage. Resulting from adopting mixed BIST technique combining paseudo-random test vector with certain test vector, multiple scan chain and compressed vector technique, an in-depth study on chip-level BIST controller technique is done, thereby raising a design proposal of specific function module. Owing to the Quartus II role in emulating to the design, the design can meet the self-test demand of avionic equipment malfunction.

Key words: controller, Build-in-Self-Test(BIST), chip-level, multiple scan chain, compressed vector

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