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计算机工程 ›› 2011, Vol. 37 ›› Issue (23): 223-225. doi: 10.3969/j.issn.1000-3428.2011.23.076

• 工程应用技术与实现 • 上一篇    下一篇

基于SystemVerilog的NoC测试平台

柯夏志,张 颖   

  1. (南京航空航天大学电子信息工程学院,南京 210016)
  • 收稿日期:2011-05-16 出版日期:2011-12-05 发布日期:2011-12-05
  • 作者简介:柯夏志(1983-),男,硕士,主研方向:集成电路设计,片上网络;张 颖,讲师、博士研究生
  • 基金资助:
    南京航空航天大学基本科研业务费专项科研基金资助项目(NS2010115)

NoC Testbench Based on SystemVerilog

KE Xia-zhi, ZHANG Ying   

  1. (College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China)
  • Received:2011-05-16 Online:2011-12-05 Published:2011-12-05

摘要: 针对片上网络(NoC)验证效率不高的问题,依据验证方法学,利用SystemVerilog语言的优势,构建一个由覆盖率驱动并受约束的随机分层NoC测试平台。在不同拓扑结构和流量分布下,对NoC进行性能评估,结果证明该测试平台具备较强的通用性、适应性和扩展性,能有效地提高验证效率。

关键词: SystemVerilog语言, 片上网络, 验证方法学, 测试平台, 功能覆盖率

Abstract: For solving the low efficiency of Network on Chip(NoC) verification, this paper constructs the coverage-driven constrained random and hierarchical NoC testbench based on the Verification Methodology Manual(VMM) and application of SystemVerilog. Results of NoC performance evaluation with heterogeneous topologies or traffic distributions show that the testbench is superior in generality, has good adaptability, scalability , and can effectively improves the verification efficiency.

Key words: SystemVerilog language, Network on Chip(NoC), Verification Methodology Manual(VMM), testbench, functional coverage rate

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