摘要: 针对片上网络(NoC)验证效率不高的问题,依据验证方法学,利用SystemVerilog语言的优势,构建一个由覆盖率驱动并受约束的随机分层NoC测试平台。在不同拓扑结构和流量分布下,对NoC进行性能评估,结果证明该测试平台具备较强的通用性、适应性和扩展性,能有效地提高验证效率。
关键词:
SystemVerilog语言,
片上网络,
验证方法学,
测试平台,
功能覆盖率
Abstract: For solving the low efficiency of Network on Chip(NoC) verification, this paper constructs the coverage-driven constrained random and hierarchical NoC testbench based on the Verification Methodology Manual(VMM) and application of SystemVerilog. Results of NoC performance evaluation with heterogeneous topologies or traffic distributions show that the testbench is superior in generality, has good adaptability, scalability , and can effectively improves the verification efficiency.
Key words:
SystemVerilog language,
Network on Chip(NoC),
Verification Methodology Manual(VMM),
testbench,
functional coverage rate
中图分类号:
柯夏志, 张颖. 基于SystemVerilog的NoC测试平台[J]. 计算机工程, 2011, 37(23): 223-225.
KE Jia-Zhi, ZHANG Ying. NoC Testbench Based on SystemVerilog[J]. Computer Engineering, 2011, 37(23): 223-225.