摘要： 研究并设计一款RISC处理器，从架构设计、电路设计、芯片后端设计多个层次保证其高性能、低功耗的特点。在架构设计层面，通过扩展寄存器堆来提升数据交互的局部性并降低对存储器的访问次数。在电路设计层面，利用动态门控时钟技术对乘除法模块和寄存器堆进行高效的时钟控制。在芯片后端设计层面，分析并比较TSMC 65 nm中GP和LP 2种工艺库，采用多阈值设计流程进一步提高处理器的速度并降低功耗。测试结果表明，与其他平台下的性能结果相比，该处理器可以将RS前向纠错解码算法的吞吐率提高4倍~70倍。

关键词: 高性能低功耗处理器, 扩展寄存器, 门控时钟, 65 nm工艺, 多阈值

Abstract: This paper presents the design of a high performance lower power RISC processor from architecture level, circuit level and backend design level. In architecture level, the processor is cache-free and register file extended to improve data locality and reduce memory accesses. In circuit level, gating clock technology is used to control MDU and register file to reduce power, and in backend level, this paper analyzes and compares GP and LP processes in TSMC 65 nm, and uses multi-threshold flow to increase speed and reduce power. Test results show that the processor can make throughput rate of RS forward error correction decoding increase 4 times~70 times, compared with other platforms.

Key words: high performance and lower power processor, extended register, gating clock, 65 nm technology, multi-threshold

中图分类号: 

• TP391