计算机工程 ›› 2012, Vol. 38 ›› Issue (21): 245-248.doi: 10.3969/j.issn.1000-3428.2012.21.065

• 工程应用技术与实现 • 上一篇    下一篇

面向无线局域网安全领域的片上网络多核架构

王 帅,韩 军,李 阳,曾晓洋   

  1. (复旦大学专用集成电路与系统国家重点实验室,上海 201203)
  • 收稿日期:2012-02-13 出版日期:2012-11-05 发布日期:2012-11-02
  • 作者简介:王 帅(1986-),男,硕士研究生,主研方向:多核SoC系统设计;韩 军,助理研究员;李 阳,硕士研究生;曾晓洋,教授、博士生导师
  • 基金项目:
    国家自然科学基金资助项目(60776028);教育部科学技术研究基金资助重点项目(109055)

NoC Multicore Architecture for WLAN Security Domain

WANG Shuai, HAN Jun, LI Yang, ZENG Xiao-yang   

  1. (State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China)
  • Received:2012-02-13 Online:2012-11-05 Published:2012-11-02

摘要: 在计算机系统和通信网络中,安全协议和密码算法用于保护敏感信息,但如何快速计算上述协议和算法成为难题。为此,提出一种面向无线局域网安全领域的片上网络多核架构。该片上网络架构包括4个类MIPS的精简指令集处理器和12个面向安全领域的专用指 令集处理器(ASIP)。每个ASIP中含有一个改进的并行查找表用来加速高级加密标准算法。该架构凭借任务并行能够获得较高的计数器模式密码块链消息完整码协议吞吐率。在SMIC 0.13 μm标准CMOS工艺下,实现该架构需要约308万等效门。实验结果表明,该系统的最大工作频率为84 MHz,能获得787 Mb/s的吞吐率。

关键词: 无线局域网, 片上网络, 高级加密标准, 并行查找表, 专用指令集处理器

Abstract: Security protocols and cryptography algorithms(ciphers) are widely used to protect the sensitive digital information in computer systems and communication networks. How to process these computation-intensive protocols and algorithms has become a crucial issue. This paper presents a Network on Chip(NoC) architecture for Wireless Local Area Network(WLAN) security domain. Four MIPS-like RISC processors and twelve security-oriented ASIPs fabricate the proposed 4×4 mesh NoC architecture. In each ASIP, the Parallel Look-Up Table (PLUT) method is implemented to accelerate Advanced Encryption Standard(AES) encryption. Moreover, task parallelism in Counter CBC-MAC Protocol(CCMP) is exploited, thus high throughput is obtained. The proposed architecture is synthesized under SMIC 0.13 μm CMOS technology and costs 3083 k-gates. Experimental results show that the system achieves a throughput of 787 Mb/s at 84 MHz.

Key words: Wireless Local Area Network(WLAN), Network on Chip(NoC), Advanced Encryption Standard(AES), Parallel Look-Up Table (PLUT), Application Specific Instruction-set Processor(ASIP)

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