[1] Rundberg P, Stenstr?m P. An All-software Thread-level Data Dependence Speculation System for Multiprocessors[J]. The Journal of Instruction-level Parallelism, 2001, (3): 1-18. [2] Hammond L, Hubbert B, Siu M, et al. The Stanford Hydra CMP[J]. IEEE Micro Magazine, 2000, 20(2): 71-84. [3] Gopal S, Vijaykumar T, Smith J, et al. Speculative Versioning Cache[C]//Proceedings of the 4th International Symposium on High-performance Computer Architecture. Washington D. C., USA: IEEE Computer Society, 1998. [4] Steffan J G, Colohan C B, Mowry T C. Architectural Support for Thread-level Data Speculation[R]. Pittsburgh, USA: School of Computer Science, Carnegie Mellon University, Technical Report: CMU-CS-97-188, 1997. [5] Steffan J G, Mowry T C. The Potential for Thread-level Data Speculation in Tightly-coupled Multiprocessor[R]. Toronto, Canada: Computer Science Research Institute, University of Toronto, Technical Report: CSRI-TR-350, 1997. [6] Steffan J G, Colohan C B. A Scalable Approach to Thread-level Speculation[C]//Proceedings of the 27th Annual International Symposium on Computer Architecture. [S. 1.]: IEEE Press, 2000. [7] Steffan J G, Colohan C B, Zhai A, et al. Improving Value Com- munication for Thread-level Speculation[C]//Proceedings of the 8th International Symposium on High-performance Computer Architecture. [S. 1.]: IEEE Press, 2000: 65-75. [8] Steffan J G, Colohan C B, Zhai A, et al. The STAMPede Approach to Thread-level Speculation[J]. ACM Transactions on Computer Systems, 2005, 23(3): 253-300. [9] Austen M, Woong C J, Hassan C, et al. Characterization of TCC on Chip-multiprocessors[C]//Proceedings of the 4th International Conference on Parallel Architectures and Compilation Techniques. [S. 1.]: IEEE Press, 2003. [10] Hammond L, Wong V, Chen M. Transactional Memory Coherence and Consistency[C]//Proceedings of the 31st Annual International Symposium on Computer Architecture. [S. 1.]: IEEE Press, 2004. [11] Hammond L, Brian D C, Vicky W, et al. Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software[J]. IEEE Micro, 2004, 24(6): 92-103. [12] Hammond L, Carlstrom B D, Wong V, et al. Programing with Transactional Coherence and Consistence(TCC)[C]//Proceedings of ASPLOS’04. [S. 1.]: IEEE Press, 2004. [13] Hammond L, Willey M, Olukotun K. Data Speculation Support for a Chip Multiprocessor[C]//Proceedings of the 8th Int’l Conf. on Architectural Support for Programming Languages and Operating Systems. [S. 1.]: IEEE Press, 1998. [14] Olukotun K, Hammond L, Willey M. Improving the Performance of Speculatively Parallel Applications on the Hydra CMP[C]// Proceedings of 1999 Int’l Conf. on Supercomputing. [S. 1.]: IEEE Press, 1999. [15] Renau J, Fraguela B, Tuck J, et al. SESC Simulator[EB/OL]. (2005-10-20). http://sesc.sourceforge.net. [16] 刘 园. 高效的线程级推测及事务执行模型研究[D]. 合肥: 中国科学技术大学, 2007.
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