摘要： 为提高现场可编程门阵列(FPGA)静态时序分析模块的仿真精度，提出一种累积频数仿真输入方法，基于此建立FPGA互连资源时序库，采用统计分析的方法对跳变时间进行累积频数分析。实验结果表明，该方法创建的互连资源时序库能够有效减小线性误差，提高仿真精度，并且与传统的均匀仿真输入方法相比，其仿真误差降至8.23%。

关键词: 现场可编程门阵列, 静态时序分析, 统计方法, 累积频数, 正值率, 互连资源库

Abstract: This paper presents a statistical method to build up interconnect timing library of Static Timing Analysis(STA) to improve the accuracy of the simulation result of Field Programmable Gate Array(FPGA) STA module. The timing library based on the method of cumulative frequency method can get a better result compared with linear simulation input library. Simulation error can be reduced to 8.23%, which is far smaller than the traditional linear simulation input library.

Key words: Field Programmable Gate Array(FPGA), Static Timing Analysis(STA), statistical method, cumulative frequency, Positive Ratio(PR), interconnect resource library

中图分类号: 

• TP312