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计算机工程 ›› 2013, Vol. 39 ›› Issue (5): 92-95,105. doi: 10.3969/j.issn.1000-3428.2013.05.019

• 体系结构与软件技术 • 上一篇    下一篇

一种高效纹理映射单元的硬件体系结构设计

赵国宇a,郭 炜b,常轶松b,魏继增b   

  1. (天津大学 a. 电子信息工程学院;b. 计算机科学与技术学院,天津 300072)
  • 收稿日期:2012-05-15 出版日期:2013-05-15 发布日期:2013-05-14
  • 作者简介:赵国宇(1988-),男,硕士研究生,主研方向:嵌入式图形处理;郭 炜,研究员;常轶松,博士研究生;魏继增,讲师
  • 基金资助:
    国家自然科学基金资助项目(61070136);教育部博士点专项科研基金资助项目(20110032120037, 20100032110041)

An Efficient Hardware Architecture Design of Texture Mapping Unit

ZHAO Guo-yu a, GUO Wei b, CHANG Yi-song b, WEI Ji-zeng b   

  1. (a. School of Electronic Information Engineering; b. School of Computer Science and Technology, Tianjin University, Tianjin 300072, China)
  • Received:2012-05-15 Online:2013-05-15 Published:2013-05-14

摘要: 针对嵌入式纹理映射过程中处理速度慢和存储带宽对系统性能制约等问题,提出一种专用纹理映射单元体系结构,对单精度浮点除法器和纹理Cache进行优化设计。采用较小查找表结合二次多项式逼近算法实现浮点除法运算,根据纹理采样的不同方式,对纹理Cache的映射方式在直接映射、两路组关联和四路组关联之间进行动态配置。对纹理映射单元在SMIC0.13 μm CMOS工艺下进行仿真,结果表明,纹理映射模块工作主频可达313 MHz,对于480×640像素,帧率可达 51 f/s,能够满足移动设备对实时渲染的需求。

关键词: 纹理映射, 透视投影, 纹理Cache, 纹理采样, 单精度浮点除法器

Abstract: This paper presents a dedicated architecture of texture mapping unit with an optimized design of single-precision floating-point divider and texture Cache, against the processing speed and memory bandwidth problem. It uses a small look-up table with quadratic polynomial approximation algorithm to achieve floating-point division. According to different sampling methods, it configures Cache mapping strategy among direct mapping, two-way set associative mapping and four-way set associative mapping. The design of the texture mapping unit is synthesized under SMIC0.13 μm CMOS process technology. Experimental results show that the design can achieve frame rate up to 51 f/s for 480×640 resolution at frequency up to 313 MHz, it is efficient for real time rendering for mobile devices.

Key words: texture mapping, perspective projection, texture Cache, texture sampling, single-precision floating-point divider

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