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计算机工程 ›› 2013, Vol. 39 ›› Issue (8): 74-76,82. doi: 10.3969/j.issn.1000-3428.2013.08.015

• 体系结构与软件技术 • 上一篇    下一篇

周期精确/位精确的Cache事务级建模方法

孙铭泽,郭 炜,周红月,魏继增   

  1. (天津大学计算机科学与技术学院,天津 300072)
  • 收稿日期:2012-02-25 出版日期:2013-08-15 发布日期:2013-08-13
  • 作者简介:孙铭泽(1988-),男,硕士研究生,主研方向:电子系统级高层次建模;郭 炜,教授;周红月,硕士研究生;魏继增,讲师、博士
  • 基金资助:
    天津市应用基础及前沿技术研究计划基金资助重点项目“高可信密码片上系统的关键技术研究”(11JCZDJC1580)

Cycle-accurate/Bit-accurate Cache Transaction Level Modeling Approach

SUN Ming-ze, GUO Wei, ZHOU Hong-yue, WEI Ji-zeng   

  1. (School of Computer Science and Technology, Tianjin University, Tianjin 300072, China)
  • Received:2012-02-25 Online:2013-08-15 Published:2013-08-13

摘要: 对于片上系统(SoC)架构设计,寄存器传送级建模仿真速度慢,而采用C语言建模达不到所需的精度要求。针对上述问题,基于电子系统级(ESL)设计方法,提出一种通用的周期精确/位精确的高速缓存(Cache)事务级模型。该模型面向外部接口和内部逻辑分别采用不同的抽象层次进行建模,并构建基于ESL设计的SoC,实现软硬件协同设计。实验结果表明,集成Cache模块的仿真平台运行相应程序所需周期数大幅减少,可达到既定的精度要求。

关键词: 高速缓存, 电子系统级设计, 事务级建模, 片上系统架构设计, 周期精确, 软/硬件协同设计

Abstract: For System on Chip(SoC) architecture design, the simulation speed of Register Transfer Level(RTL) modeling is slow, and system modeling using C language lacks of enough accuracy. To solve these problems, this paper presents a Cache Transaction Level Modeling(TLM) method with cycle-accurate and bits-accurate, using electronic system level design methodology. In the model, different abstraction layers are adopted in the external interfaces and internal logic. The SoC is constructed based on the Electronic System Level(ESL) design, and realizes the S/H co-design. Experimental results show that the simulation platform with the Cache model is significantly reduced in the number of cycles when running the corresponding program, and achieves the established accuracy requirements.

Key words: Cache, Electronic System Level(ESL) design, Transaction Level Modeling(TLM), System on Chip(SoC) architecture design, cycle-accurate, software/hardware co-design

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