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计算机工程

• 移动互联与通信技术 • 上一篇    下一篇

3D NoC网络架构设计

谢 林a,b,潘红兵a,b,张宇昂a,b,韩 峰a,b,李 丽a,b,何书专a,b   

  1. (南京大学 a. 微电子设计研究所;b. 江苏省光电信息功能材料重点实验室,南京 210093)
  • 收稿日期:2012-03-30 出版日期:2013-09-15 发布日期:2013-09-13
  • 作者简介:谢 林(1990-),男,硕士研究生,主研方向:多核处理器;潘红兵,副教授、博士;张宇昂,博士研究生;韩 峰, 硕士研究生;李 丽,教授、博士;何书专,工程师
  • 基金资助:
    国家自然科学基金资助项目(61176024)

Design of 3D NoC Network Architecture

XIE Lin a,b, PAN Hong-bing a,b, ZHANG Yu-ang a,b, HAN Feng a,b, LI Li a,b, HE Shu-zhuan a,b   

  1. (a. Institute of VLSI Design; b. Jiangsu Provincial Key Laboratory of Photonic & Electronic Materials Sciences and Technology, Nanjing University, Nanjing 210093, China)
  • Received:2012-03-30 Online:2013-09-15 Published:2013-09-13

摘要: 在三维片上网络(3D NoC)设计中,层与层之间通信机制的优劣将影响整个3D NoC系统的性能。为此,在GEMS仿真平台基础上,提出一种低硬件资源消耗、高性能的总线架构,改进路由设计,构造基于总线的3D NoC的路由器。实验结果表明,该架构可提高常见算法的加速比,改善系统的整体性能。

关键词: 三维片上网络, 架构, GEMS多核仿真平台, 总线, 路由器

Abstract: In the Three-dimensional Network on Chip(3D NoC) design, the pros of the communication mechanism between the layers will affect the performance of the entire 3D NoC system. In order to solve the above problem, this paper makes some improvements based on the traditional three-dimensional interconnect. For 3D NoC communication problems, this paper proposes a low hardware resource consumption, high performance bus architecture under GEMS simulation platform. It improves routing design, and bus-based 3D NoC router. Experimental results show that the architecture can increase speed-up ratio of common algorithms, and improve overall system performance.

Key words: Three-dimensional Network on Chip(3D NoC), architecture, GEMS multi-core simulation platform, bus, router

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