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计算机工程

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基于OMAP处理器的核间通信机制设计与实现

冯 强1,2,胡 毅2,3,于 东2,3,陆小虎1,2   

  1. (1. 中国科学院大学,北京 100049;2. 中国科学院沈阳计算技术研究所高档数控国家工程研究中心,沈阳 110168;3. 沈阳高精数控技术有限公司,沈阳 110168)
  • 收稿日期:2013-01-14 出版日期:2014-04-15 发布日期:2014-04-14
  • 作者简介:冯 强(1987-),男,硕士研究生,主研方向:数控技术;胡 毅,副研究员、博士;于 东,研究员、博士、博士生导师;陆小虎,硕士研究生。
  • 基金资助:
    国家科技重大专项基金资助项目“开放式数控系统支撑技术创新平台建设”(2011ZX04016-071)。

Design and Implementation of Inter-core Communication Mechanism Based on OMAP Processor

FENG Qiang  1,2, HU Yi  2,3, YU Dong  2,3, LU Xiao-hu  1,2   

  1. (1. University of Chinese Academy of Sciences, Beijing 100049, China; 2. National Engineering Research Center for High-end Numerical Control, Shenyang Institute of Computing Technology, Chinese Academy of Sciences, Shenyang 110168 China; 3. Shenyang High Precision Numerical Control Technology Co., Ltd., Shenyang 110168, China)
  • Received:2013-01-14 Online:2014-04-15 Published:2014-04-14

摘要: 为满足嵌入式多核数控系统高速、高精的应用需求,针对现有多核通信延迟过高、通信数据量过小等不足,研究基于ARM与DSP双核架构嵌入式数控系统,设计并实现一种基于该数控系统平台的多核数据通信机制。该通信机制基于共享内存实现,包括硬件驱动实现、内存划分、通信同步、共享缓存池建立以及通信协议搭建等关键部分。针对双核间数据传输延迟和数据传输量 2个影响系统性能的重要参数开展实验测试,并于实际数控系统环境进行应用测试,结果表明,该通信方法可满足ARM与DSP双核架构的嵌入式数控系统2 MB数据通信量与20 ms通信延迟的性能需求。

关键词: 嵌入式数控系统, 异构处理器, 多核通信, 共享内存, 通信延迟

Abstract: In order to meet the application needs of embedded multi-core, high-speed and high-precision numerical control system, owing to the high latency, low communication capacity of current multi-core communication, this paper studies the design of embedded numerical control system based on ARM and DSP dual-core architecture, designs and implements a multi-core data communication mechanism based on the numerical control system platform. The communication mechanism is based on shared memory, including hardware driver realization, memory division, communication synchronization and the establishment of a shared cache pool and communication protocol. It completes the measurement of dual-core data transmission latency and data transmission capacity, which affects system performance, and carries out the application test. The results prove that this design can meet the performance requirements of 2 MB data communications volume and 20 ms communication delay of the embedded ARM and DSP dual-core architecture numerical control system.

Key words: embedded numerical control system, heterogeneous processor, multi-core communication, shared memory, communication delay

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