摘要： 针对传统定向测试效率较低且容易遗漏边界条件，以及测试平台扩展性、移植性差等问题，利用SystemVerilog的面向对象特性、随机约束求解机制以及覆盖率统计机制，提出一种快速搭建覆盖率驱动的随机测试平台的方法。采用面向对象方法对指令集建模，同时定义功能覆盖点和交叉覆盖率，并对随机约束规则进行描述，利用SystemVerilog的约束求解机制在覆盖率驱动下生成大量的测试指令码。对“银河飞腾”高性能DSP芯片指令集进行验证，结果表明，与定向测试相比，随机测试的寄存器和数据通路覆盖率提高50%，操作数覆盖率提高90%以上，交叉覆盖率提高75%以上，同时功能覆盖率能在较短的时间内达到预期值，从而缩短验证周期。
关键词:
SystemVerilog语言,
随机测试,
覆盖率驱动,
约束描述,
面向对象编程,
验证平台
Abstract: The traditional directed test is not efficient and easy to miss the boundary cases, and the scalability and the portability of test platform is poor. Aiming at these problems, by using SystemVerilog object-oriented features, constrained-random solving mechanism and coverage mechanism, this paper puts forward a fast method to build a coverage-driven random test platform. It uses object-oriented method to model the instruction set. It defines functional coverage points and cross-coverage points, and describes random constraint rules. It uses SystemVerilog constraint solving mechanism to generate a large number of test scripts. The verification for instruction set of “YHFT” DSP chip shows that the registers and data path coverage are improved by 50%, the operand coverage is improved by more than 90%, and the cross coverage is improved by more than 75% compared with the directed test. And the function coverage can reach the expected value in short cycles which improves the coverage rate, and shorten the verification cycles.
Key words:
SystemVerilog language,
random test,
coverage-driven,
constraint description,
object-oriented programming,
verification platform
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