摘要： 在嵌入式视频处理领域,针对视频实时性要求高的特点,提出一种基于现场可编程门阵列(FPGA)的多路视频合成和去噪方法,包含四路视频合成一路视频的具体实现方案,以及对合成后的一路视频进行中值滤波的去噪算法,使用DDR2 SDRAM 作为视频的帧缓存,设计中值滤波算法的硬件结构和逻辑结构。系统设计采用Verilog 语言进行描述,并在Xilinx 的FPGA 上进行逻辑综合和硬件测试。实验结果表明,该方法利用FPGA 实现 了硬件并行和流水线技术,可保证视频的实时处理。

关键词: 现场可编程门阵列, Verilog 语言, 多路视频合成, 去噪, 中值滤波, 实时性

Abstract: In the field of embedded video processing,due to the critical real-time requirement of the video,this paper proposes an FPGA-based multi-channel video compositing and de-noising method. This paper contains concrete realization scheme that four-channel video is combined to one-channel video and de-noising algorithm of median filtering to onechannel video. The video is buffered by DDR2 SDRAM,and the hardware structure and logic structure of median filtering algorithm are demonstrated. The Verilog language is used to describe the overall system design,and a logic synthesis and hardware test is implemented on Xilinx FPGA. Experimental results show that the design uses the FPGA’ s hardware parallelism and pipeline technology,and the performance of real-time processing for the video is entirely achieved.

Key words: Field Programmable Gate Array(FPGA), Verilog language, multi-channel video compositing, de-noising, median filtering, real-time

中图分类号: 

• TP391