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计算机工程

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用于DVFS 片上系统的全数字SARDLL 设计

徐太龙1,薛 峰2,高先和1,蔡志匡3,韩少宇4,胡学友1,陈军宁4   

  1. (1. 合肥学院电子信息与电气工程系,合肥230601;2. 安徽三联学院电子电气工程学院,合肥230601; 3. 南京邮电大学电子科学与工程学院,南京210046;4. 安徽大学电子信息工程学院,合肥230601)
  • 收稿日期:2014-08-20 出版日期:2015-04-15 发布日期:2015-04-15
  • 作者简介:徐太龙(1982 - ),男,讲师、博士,主研方向:集成电路设计,数字信号处理;薛 峰,讲师、硕士;高先和(通讯作者),副教授、硕 士;蔡志匡,讲师、博士;韩少宇,硕士研究生;胡学友,副教授、博士;陈军宁,教授、博士。
  • 基金资助:
    安徽省教育厅自然科学研究基金资助重点项目(KJ2014A211);合肥学院重点建设学科基金资助项目(2014xk06)。

Design of All Digital SARDLL for DVFS System-on-Chip

XU Tailong 1,XUE Feng 2,GAO Xianhe 1,CAI Zhikuang 3,HAN Shaoyu 4,HU Xueyou 1,CHEN Junning 4   

  1. (1. Department of Electronic Information and Electrical Engineering,Hefei University,Hefei 230601,China; 2. School of Electronic and Electrical Engineering,Anhui Sanlian University,Hefei 230601,China; 3. College of Electronic Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210046,China; 4. School of Electronic Information Engineering,Anhui University,Hefei 230601,China)
  • Received:2014-08-20 Online:2015-04-15 Published:2015-04-15

摘要: 针对动态电压/ 频率调整系统芯片中时钟同步问题,设计一个具有宽工作频率范围和固定锁定周期的快速锁定全数字逐次逼近延时锁定环,采用改进的可复位数字控制延时线方法,在减小面积和提高最高工作频率的同时,有效地解决传统全数字逐次逼近延时锁定环的谐波锁定和零延时陷阱问题。整个延时锁定环采用TSMC-65 nm CMOS 工艺标准单元库实现,仿真结果表明,在典型工艺角和25 ℃ 情况下,工作频率范围为250 MHz ~ 2 GHz,锁定时间为固定的18 个输入时钟周期,当电源电压为1. 2 V、输入时钟频率为2 GHz 时,功耗为0. 4 mW。

关键词: 动态电压/ 频率调整, 延时锁定环, 时钟偏差, 片上系统, 锁定时间, 谐波锁定, 零延时陷阱

Abstract: An all digital fast-locking Successive Approximation Register-controlled Delay-Locked Loop(SARDLL) with wide-range operating frequency and constant acquisition cycles is presented for the clock synchronization of Dynamic Voltage / Frequency Scaling (DVFS) System-on-Chip (SoC). The improved resettable Digitally Controlled Delay Line (DCDL) scheme is adopted to effectively solve the harmonic lock problem and zero-delay problem of the conventional all digital SARDLL,meanwhile reduces the hardware overhead and increases the maximum operating frequency. The presented all digital SARDLL is implemented using the TSMC-65 nm CMOS standard cell library. Based on the typical corner and 25℃,the post-layout simulation results show that the operating frequency range is from 250 MHz to 2 GHz,the lock time is 18 cycles of the input clock signal and the power consumption is 0. 4 mW at 2 GHz and 1. 2 V supply voltage.

Key words: Dynamic Voltage / Frequency Scaling(DVFS), Delay-Locked Loop(DLL), clock skew, System-on-Chip (SoC), lock time, harmonic lock, zero-delay trap

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