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计算机工程

• 体系结构与软件技术 • 上一篇    下一篇

基于双TLB的二进制翻译访存性能优化

李晖  1,王振华  2,3,靳国杰  3,4   

  1. (1.中国南方电网有限责任公司,广州 510623; 2.中国科学院大学计算机与控制工程学院,北京 100049; 3.中国科学院计算技术研究所,北京 100190; 4.龙芯中科技术有限公司,北京 100190)
  • 收稿日期:2015-03-16 出版日期:2015-12-15 发布日期:2015-12-15
  • 作者简介:李晖(1983-),男,工程师、博士,主研方向:计算机体系结构;王振华,硕士研究生;靳国杰,高级工程师、博士。

Optimization of Binary Translation Memory Access Performance Based on Dual-TLB

LI Hui  1,WANG Zhenhua  2,3,JIN Guojie  3,4   

  1. (1.China Southern Power Grid Limited Liability Company,Guangzhou 510623,China; 2.School of Computer and Control Engineering,University of Chinese Academy of Sciences,Beijing 100049,China;3.Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China; 4.Loongson Technology Co., Ltd.,Beijing 100190,China)
  • Received:2015-03-16 Online:2015-12-15 Published:2015-12-15

摘要: 现有二进制翻译系统主要采用纯软件的方法实现访存指令模拟,用于目标访存指令的翻译后代码规模过高,导致模拟效率低下。针对该问题,提出一种高效的龙芯二进制翻译系统,设计一种双翻译后备缓冲(TLB)结构,通过在CPU核中新增一个专门用于转换宿主机地址的硬件TLB,实现由硬件直接进行地址转换,并通过降低用于X86访存指令的翻译后代码规模减少模拟开销。实验结果表明,与采用纯软件模拟方法的二进制翻译系统相比,优化后的内存拷贝性能提高约100倍,模拟X86 Linux内核的启动时间缩短19.12%。

关键词: 指令集架构, 二进制翻译, 翻译后备缓冲, 命中率, 龙芯处理器

Abstract: Current binary translation systems mainly simulate memory access instructions by a pure-software method.Memory emulation is the bottleneck of the performance of the binary translation system due to the large number of translated instructions.This paper introduces the Loongson binary translation system,which implements a new TLB on chip to perform the address translation directly.It reduces the simulation spending by reducing the translated code size for X86 memory access instructions.Experimental result shows,the performance of memory copy is improved for 100 times,the simulation X86 Linux kernel booting time is shorten by 19.12%,compared with binary translation system using pure-software simulation method.

Key words: Instruction Set Architecture(ISA), Binary translation, Translation Look-aside Buffer(TLB), hit rate, Loongson processor

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