计算机工程 ›› 2017, Vol. 43 ›› Issue (12): 60-64.doi: 10.3969/j.issn.1000-3428.2017.12.011

• 体系结构与软件技术 • 上一篇    下一篇

一种支持多个FIQ的向量中断控制器设计

朱席鼎 1,张涛 1,余梓奇 2,胡知川 1   

  1. (1.武汉科技大学 信息科学与工程学院,武汉 430081; 2.中国电子科技集团公司第三十二研究所,上海 201808)
  • 收稿日期:2016-11-02 出版日期:2017-12-15 发布日期:2017-12-15
  • 作者简介:朱席鼎(1991—),男,硕士研究生,主研方向为数字集成电路设计、嵌入式系统;张涛,教授;余梓奇、胡知川,硕士研究生。
  • 基金项目:
    冶金自动化与检测技术教育部工程研究中心开放基金(MADT201607);湖北省教育厅科学技术研究计划青年人才项目(Q20161105)。

A Design of Vectored Interrupt Controller Supporting Multiple FIQ

ZHU Xiding  1,ZHANG Tao  1,YU Ziqi  2,HU Zhichuan  1   

  1. (1.School of Information Science and Engineering,Wuhan University of Science and Technology,Wuhan 430081,China; 2.The 32nd Research Institute of China Electronics Technology Group Corporation,Shanghai 201808,China)
  • Received:2016-11-02 Online:2017-12-15 Published:2017-12-15

摘要: 为降低多个中断源被分配为快速中断请求(FIQ)时的时间开销,设计一种用于FIQ中断源识别和优先级仲裁的向量中断控制器。采用Verilog语言完成硬件描述,通过Modelsim仿真和FPGA验证,实现基于SMIC 0.13 μm CMOS工艺的综合布局布线工作。仿真和验证结果表明,该向量中断控制器的面积为0.107 mm2,平均功耗为3.56 mW,工作频率为80 MHz,可满足移动通信宽带射频片上系统芯片的实时性需求。

关键词: 向量中断控制器, 快速中断请求, 中断优先级, 片上系统, 先进高性能总线

Abstract: To reduce the time overhead of assigning multiple Fast Interrupt Request(FIQ),a vectored interrupt controller for FIQ interrupt source identification and priority arbitration is designed.It is described by Verilog-HDL.Modelsim simulation and FPGA verification are also passed.Synthesis is completed with SMIC 0.13 μm CMOS technology,as well as place and route.Simulation and verification results show that the area is 0.107 mm2,the average power is 3.56 mW and the frequency is 80 MHz.This design can meet the real time demand of the chip in mobile communication RF SoC.

Key words: Vectored Interrupt Controller(VIC), Fast Interrupt Request(FIQ), interrupt priority level, System on Chip(SoC), Advanced High-performance Bus(AHB)

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