摘要: 设计一款适用于高性能数字信号处理器的16位加法器。该加法器结合条件进位选择和条件“和”选择加法器的特点,支持可重构,可以进行2个16位数据或者4个8位数据的加法运算,同时对其进位链进行优化。相对于传统的条件进位选择加法器,在典型工作条件下,采用0.18 m工艺库标准单元,其延时降低46%,功耗降低5%。
关键词:
条件进位选择加法器,
条件“和”选择加法器,
可重构加法器
Abstract: This paper presents the design of a high performance re-configurable 16-bit adder, which is well suitable for digital signal processor. The adder can add two 16-bit operands or four 8-bit operands. It is a hybrid of Conditional Carry Select adder(CCS) and Conditional Sum Select adder(CSS) with which the carry chain is also optimized. Simulation results show that the delay is reduced by 46% and the power is 5% lower compared with the general CCS under typical conditions with standard cell using 0.18 m technology.
Key words:
Conditional Carry Select adder(CCS),
Conditional Sum Select adder(CSS),
re-configurable adder
中图分类号:
马 鸿;李振伟;彭思龙. 数字信号处理器中高性能可重构加法器设计[J]. 计算机工程, 2009, 35(12): 1-4.
MA Hong; LI Zhen-wei; PENG Si-long. High Performance Re-configurable Adder Design for Digital Signal Processor[J]. Computer Engineering, 2009, 35(12): 1-4.