摘要：

为提高处理器核仿真模型的效率，提出基于SimpleScalar架构对龙芯1号处理器进行虚拟处理器模型行为建模，IPC平均误差为2.3%，速度达到每秒1 000 000条指令。基于可控随机事件机制实现的总线功能模型可以为片上系统(SoC)设计提供激励主动生成方案和片上互连验证功能。实验结果证明，该方法对处理器IP仿真建模具有普适意义，能够被无缝融入SoC流程中。

关键词: IP仿真模型, SimpleScalar模拟器, 可控随机事件, 总线功能模型, 龙芯1号处理器

Abstract:

In order to improve processor core simulation modeling efficiency, a virtual processor modeling method based on SimpleScalar architecture is proposed, and the model aiming at Godson-1 processor reaches 1 000 000 per second with average IPC error of 2.3%. A controllable random event Bus Function Model(BFM) is presented, providing active stimuli generation and on-chip bus verification function for SoC design. Experimental result proves that the solution has broad applicability in processor core modeling and can be seamlessly integrated into mainstream SoC flow.

Key words: IP simulation model, SimpleScalar simulator, controllable random event, Bus Functional Model(BFM), Godson-1 processor

中图分类号: 

• TP368.1