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计算机工程 ›› 2009, Vol. 35 ›› Issue (8): 250-252. doi: 10.3969/j.issn.1000-3428.2009.08.085

• 多媒体技术及应用 • 上一篇    下一篇

H.264帧内预测的FPGA实现

单 博,张 晔,陈 浩   

  1. (哈尔滨工业大学信息工程系,哈尔滨 150001)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2009-04-20 发布日期:2009-04-20

FPGA Implementation of H.264 Intra-frame Prediction

SHAN Bo, ZHANG Ye, CHEN Hao   

  1. (Department of Information Engineering, Harbin Institute of Technology, Harbin 150001)
  • Received:1900-01-01 Revised:1900-01-01 Online:2009-04-20 Published:2009-04-20

摘要: 实现H.264实时性面临的主要障碍是计算量大,预测操作占其总计算量的30%以上。该文使用FPGA实现一种以梯度作为判据的快速帧内预测算法。该算法借助FPGA逻辑资源丰富、高速并行运算、I/O接口丰富的特点,采用多级流水线、乒乓操作的电路结构。相应的帧内预测模块结构清晰,处理速度较DSP(TMS320C6211)提高46.41倍,满足了视频图像处理的实时性要求。

关键词: 视频图像压缩, H.264标准, 帧内预测, FPGA芯片, 高速图像处理

Abstract: Computing amount is the main obstacle of meeting the real time requirement in H.264. Pre-operation occupies 30 percent of the total computing amount. This paper uses FPGA to realize a kind of intra-prediction algorithm, which decides the intra-prediction mode by the grads. This algorithm uses advantages of FPGA logic such as abundant logical element, high speed parallel computing, abundant I/O ports, and adopts circuit architecture with multilevel pipeline and ping-pong operation. The intra-frame prediction module is clear in architecture, and its processing speed is 46.41 times DSP(TMS320C6211). It meets the real time requirement of video image processing.

Key words: video image compression, H.264 standard, intra-frame prediction, FPGA chip, high-speed image processing

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