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计算机工程 ›› 2008, Vol. 34 ›› Issue (17): 153-154,. doi: 10.3969/j.issn.1000-3428.2008.17.054

• 安全技术 • 上一篇    下一篇

针对F5隐写分析算法的FPGA实现

周治平,周礼华   

  1. (江南大学通信与控制工程学院,无锡 214122)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2008-09-05 发布日期:2008-09-05

FPGA Realization of Steganalytic Algorithm Against F5

ZHOU Zhi-ping, ZHOU Li-hua   

  1. (College of Communication and Control Engineering, Jiangnan University, Wuxi 214122)
  • Received:1900-01-01 Revised:1900-01-01 Online:2008-09-05 Published:2008-09-05

摘要: 应用密钥来控制隐藏路径已成为一种趋势,随着消息长度的增加和密钥空间的增大,纯软件方式已不能满足隐写分析的实时性要求。针对依赖密钥的隐写算法F5,提出一种基于现场可编程门阵列(FPGA)的隐写分析方案。正确密钥与错误密钥产生嵌入位置的样本分布具有明显的差异,利用这一特性可以得到F5的正确密钥,从而实现密钥攻击。实验表明,消息长度超过2 000 bit时,该方案和软件攻击相比时间上能降低一个数量级。

关键词: 信息隐藏, 密钥, 隐写分析, 现场可编程门阵列

Abstract: Using stego-key to control embedding path becomes a trend. Software attack is increasingly unable to meet the real-time requirement of steganalysis as the length of secret message and the key space increases. An FPGA-based steganalysis scheme against key-dependent steganography F5 is proposed. The embedding paths produced by correct key and wrong keys have obvious difference in distribution of samples. This phenomenon can be used to get the correct stego-key of F5, thereby the attack succeeds. Experiments show that as the length of message exceeds 2 000 bit, this scheme can decrease a magnitude order of time compares with software attack.

Key words: information hiding, stego-key, steganalysis, FPGA

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