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计算机工程 ›› 2008, Vol. 34 ›› Issue (5): 36-38. doi: 10.3969/j.issn.1000-3428.2008.05.013

• 博士论文 • 上一篇    下一篇

多处理器芯片组中交叉开关的设计与性能优化

方志斌1,2,3,安学军1,3,胡 鹏1,2,3   

  1. (1. 中国科学院计算技术研究所,北京 100080;2. 中国科学院研究生院,北京 100039; 3. 中国科学院计算机系统结构重点实验室,北京 100080)
  • 收稿日期:1900-01-01 修回日期:1900-01-01 出版日期:2008-03-05 发布日期:2008-03-05

Design and Performance Optimization of Crossbar in Multi-processor Chipset

FANG Zhi-bin1,2,3, AN Xue-jun1,3, HU Peng1,2,3   

  1. (1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080; 2. Graduate School, Chinese Academy of Sciences, Beijing 100039; 3. Key Laboratory of Computer System and Architecture, Chinese Academy of Sciences, Beijing 100080)
  • Received:1900-01-01 Revised:1900-01-01 Online:2008-03-05 Published:2008-03-05

摘要: 交叉开关是交换芯片和芯片组的核心逻辑。该文设计并实现了多处理器芯片组中的交叉开关,其工作频率在FPGA布局布线后可以达到100 MHz。通过实践采样,对延迟和带宽进行测试,提出性能优化的策略,目前该交叉开关已稳定运行于龙芯2E多处理器系统中。

关键词: 交叉开关, 多处理器, 芯片组

Abstract: Crossbar is the core logic of switch and chipset. This paper designs and implements a crossbar in multi-processor chipset, and the frequency of the crossbar is up to 100 MHz after placing and routing on FPGA platform. The delay and bandwidth of the crossbar is tested based on implementation, and some optimization strategies of the crossbar are proposed. The crossbar runs in multi-processor system composed by Godson 2E CPU.

Key words: crossbar, multi-processor, chipset

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