摘要： 随着网络带宽的飞速增长和各种新的网络应用不断涌现，原有的基于通用处理器和ASIC的互联网架构已经不能满足新的需求。兼具强大处理能力和灵活可编程配置能力的网络处理器逐渐得到广泛的应用。高性能的网络处理器通常采用多个并发的处理单元进行数据平面的快速处理，这些处理单元在网络处理器中居于核心的地位。该文讨论了网络处理器中处理单元设计需要考虑的因素，设计了一种较为灵活有效的处理单元架构，并进行了FPGA原型验证，证实了该结构的可行性。

关键词: 网络处理器, 处理单元, 并行处理

Abstract: With the rapid increase in network bandwidth and emergence of various new network applications, original solutions based on general purpose processor(GPP) and application specific integrated circuit (ASIC) can not fulfill the requirements of high performance, flexibility and extensibility. Network processors are getting wide acceptance with its powerful processing ability and programmability. Almost all the network processors of high performance consist of multiple processing elements which are powerhouse for deep packet processing process packets concurrently. This paper discusses the design of processing elements, proposes a flexible yet efficient architecture for processing element, and demonstrates its feasibility through FPGA prototyping.

Key words: Network processor, Processing element, Parallel processing