摘要： 在采用基于VelociTI结构浮点DSPs流水线模式设计具有自主知识产权的数字信号处理器中，为了正确有效地实现对流水线异常的控制，提出了一种该结构流水线发生异常时的处理方法。对引起流水线异常的情况进行了合理的分类，存储器阻塞、多执行包和多周期NOP指令采用通过控制流水线寄存器的时钟信号实现控制。采用控制指令的执行条件实现了中断引起的流水线队列中部分指令的废除。对提出的方法采用VHDL语言建模设计，仿真结果验证了其正确性。

关键词: VelociTI结构, 数字信号处理器, 流水线异常

Abstract:

In order to design digital signal processor with own property right, one kind of pipeline structure of floating point digital signal processor based on VelociTI architecture is studied and a new processing method for pipeline exception is proposed. Abnormal things affecting pipeline are classified reasonably. Pipeline registers’ clock signals of pipeline registers are controlled for memory blocking, many execute packets, many cycles NOP instructions. Some instructions should be disabled when interruption occurs, this work is done by controlling execute condition of these instructions. The correctness can be confirmed by simulation results.

Key words: VelociTI architecture, DSPs, pipeline-exception

中图分类号: 

• TP331