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计算机工程 ›› 2010, Vol. 36 ›› Issue (14): 212-214. doi: 10.3969/j.issn.1000-3428.2010.14.077

• 工程应用技术与实现 • 上一篇    下一篇

基于网络处理的多核共享SDRAM控制器

武颖奇,李 康,马佩军,关 娜,史江义   

  1. (西安电子科技大学微电子学院宽禁带半导体材料与器件重点实验室,西安 710071)
  • 出版日期:2010-07-20 发布日期:2010-07-20
  • 作者简介:武颖奇(1987-),男,硕士研究生,主研方向:数字集成电路设计;李 康、马佩军,副教授、博士;关 娜,硕士研究生;史江义,副教授、博士
  • 基金资助:
    国家自然科学基金资助项目(60506020);陕西省科技厅自然科学基础研究计划基金资助项目(SJ08-ZT13)

Multi-core Sharing SDRAM Controller Based on Network Processing

WU Ying-qi, LI Kang, MA Pei-jun, GUAN Na, SHI Jiang-yi   

  1. (Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an 710071)
  • Online:2010-07-20 Published:2010-07-20

摘要: 设计一种基于网络处理的多核共享SDRAM控制器,提出分层优先级仲裁算法以提高多核访问共享内存的效率,针对IP包处理特点,给出一种基于指令控制的块数据传输机制来缩短IP包的读写延迟。在FPGA平台上进行验证,结果表明,当处理长度为64 Byte的IP包时,SDRAM控制器的读写效率能提高55%以上。

关键词: 分层优先级仲裁, 块数据传输, SDRAM控制器

Abstract: This paper designs a multi-core sharing SDRAM controller based on network processing, presents a hierarchical priority arbitration algorithm to improve the efficiency of accessing shared memory for the multi-core. For the IP packet processing features, a block data transfer mechanism based on the instruction control is presented, which can shorten the latency of processing IP packet. Priority algorithm and block data transfer mechanism are verified on FPGA platform. Results indicate that processing the IP packet of 64 Byte, SDRAM controller can improve the reading and writing efficiency by 55% at least.

Key words: hierarchical priority arbitration, block data transfer, SDRAM controller

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