摘要： 基于计算局域性原理提出评价网络性能的底层全互联率，利用该指标对TriBA拓扑结构的直接互联网络在计算速度、物理布局 2个方面进行性能分析。结果表明，TriBA的底层全互连结构可降低网络复杂度、提高通信性能，对角线VLSI布局得到的功耗相比2D Mesh结构节省了11%，该功耗优势在大规模片上多核系统中尤为明显。
关键词:
片上多核系统,
TriBA拓扑结构,
局域性,
直接互联网络,
VLSI布局
Abstract: This paper presents a lower layer full interconnection rate to evaluate network performance based on the principle of computing local property. It uses this criterion to go on performance evaluation about computing speed and physical layout of Direct Interconnection Network(DIN) of Triplet Based computer Architecture(TriBA). Result shows that lower layer full interconnection structure of TriBA can reduce network complexity and enhance communication performance, diagonal VLSI layout of TriBA saves about 11% power compared to 2D Mesh structure, this advantage of power consumption is in large scale Multi Processor System on Chip(MPSoC).
Key words:
Multi Processor System on Chip(MPSoC),
Triplet Based computer Architecture(TriBA) topology structure,
local property,
Direct Interconnection Network(DIN),
Very Large Scale Integrated circuit(VLSI) layout
中图分类号:
刘彩霞, 石峰, 乔保军, HAROON Ur Rashid, 宋红. TriBA互联拓扑结构及其性能分析[J]. 计算机工程, 2010, 36(15): 105-107.
LIU Cai-Xia, DAN Feng, JIAO Bao-Jun, HAROON Ur Rashid, SONG Gong. TriBA Interconnection Topology Structure and Its Performance Analysis[J]. Computer Engineering, 2010, 36(15): 105-107.