摘要： 采用自顶向下方法，设计实现16位精简指令集计算机架构的嵌入式微处理器核HEUSoC1，利用现场可编程门阵列片内的大量存储资源实现双端口存储器及零等待的指令和数据访问，从而保证指令的单周期执行。通过Verilog硬件描述语言实现微处理器核的RTL级描述，编写计算斐波那契数列的测试程序验证了HEUSoC1的正确性。在Xilinx Spartan2芯片上的统计结果表明，HEUSoC1的资源占用率较低，处理器最高频率约为22 MHz，适合于对功耗和性价比要求严格的嵌入式应用领域。

关键词: 嵌入式系统, 微处理器核, 精简指令集计算机, Verilog硬件描述语言, 现场可编程门阵列

Abstract: This paper describes the topdown design and implementation embedded microprocessor core HEUSoC1 of 16 bit Reduced Instruction Set Computer(RISC) architecture, it achieves twoport memory and zero latency access of instruction and data by using the large amount of onchip storage resources of Field Programmable Gate Array(FPGA). This characteristic guarantees that all of the instructions are executed in single machine cycle. HEUSoC1 is implemented at RTL level with Verilog Hardware Description Language(HDL). Fibonacci number calculation is programmed in assembly language to verify the validity of HEUSoC1. Resource utilization summary results show that the HEUSoC1 is resourceefficient, its highest processor frequency is approximate 22 MHz on the Xilinx Spartan2, and it is suitable for embedded application which demands low power consumption and high costperformance ratio.

Key words: embedded system, microprocessor core, Reduced Instruction Set Computer(RISC), Verilog Hardware Description Language(HDL), Field Programmable Gate Array(FPGA)

中图分类号: 

• N945.15