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计算机工程 ›› 2011, Vol. 37 ›› Issue (11): 257-259,274. doi: 超宽带;交织器;正交频分复用;标准兼容;现场可编程门阵列

• 工程应用技术与实现 • 上一篇    下一篇

超宽带无线通信系统中兼容性交织器设计

李晨熙,刘 亮,叶 凡   

  1. (复旦大学专用集成电路与系统国家重点实验室微纳电子科技创新平台,上海 201203)
  • 收稿日期:2010-12-18 出版日期:2011-06-05 发布日期:2011-06-05
  • 作者简介:李晨熙(1984-),男,硕士研究生,主研方向:超带宽无线通信系统,数字集成电路设计;刘 亮,博士研究生;叶 凡,讲师
  • 基金资助:
    国家科技重大专项基金资助项目“载波体制超宽带高速无线通信芯片研发与应用示范”(2009ZX03006-007-01),“超宽带设备的技术规范和性能评测”(2009ZX03006-009)

Design of Compatibility Interleaver in Ultra Wide Band Wireless Communication System

LI Chen-xi, LIU Liang, YE Fan   

  1. (State Key Lab of Application Specific Integrated Circuit & System, Micro/Nano-Electronics Science and Technology Innovation Platform, Fudan University, Shanghai 201203, China)
  • Received:2010-12-18 Online:2011-06-05 Published:2011-06-05

摘要: 设计一种应用于超宽带(UWB)无线通信系统的交织器,采用双端口随机存取存储器结合地址发生器的结构,实现多波段正交频分复用和双载波正交频分复用2种标准下比特交织的兼容。相比只适用于单一标准的交织器,该交织器在查找表数目增加4.5%、寄存器数目增加1.8%的情况下,工作主时钟达到132 MHz,数据吞吐率达到最大1.42 Gb/s,满足UWB系统要求。

关键词: 超宽带, 交织器, 正交频分复用, 标准兼容, 现场可编程门阵列

Abstract: This paper designs a interleaver which is used in Ultra Wide Band(UWB) system. The interleaver is based on the structure of two port Random Access Memory(RAM) and address generator, it can be compatible with standards of Multi Band-Orthogonal Frequency Division Multiplexing(MB-OFDM) and Dual Carrier-Orthogonal Frequency Division Multiplexing(DC-OFDM). To compare with the interleaver applied to only one standard, this interleaver just increase 4.5% and the registers increase 1.8%. The main clock frequency is 132 MHz and the max throughput is 1.42 Gb/s, and it meets the requirement of UWB system.

Key words: Ultra Wide Band(UWB), interleaver, Orthogonal Frequency Division Multiplexing(OFDM), standard compatible, Field Programmable Gate Array(FPGA)

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