摘要：

自反馈测试方法TVAC在时序电路中的应用研究还处于起步阶段。为此，研究其在同步全扫描时序电路测试中的应用，提出2种测试结构，并对ISCAS89电路进行实验。实验结果表明，与加权伪随机方法和循环自测试方法相比，该方法可用较少测试矢量达到较高故障覆盖率。

关键词: 内建自测试, 全扫描测试, 加权随机测试, 循环自测试路径, 自反馈测试

Abstract:

Test Vectors Applied by Circuit-under-test itself(TVAC) is a new Built-in Self-test(BIST) scheme. Two different TVAC structures for synchronous full scan sequential circuits are presented. Experimental results on ISCAS89 benchmark circuits demonstrate that, compared with the weighted-random-pattern test and Circular Self-test Path(CSTP) method, the TVAC scheme can reach higher fault coverage with smaller test vectors.

Key words: Built-in Self-test(BIST), full scan test, weighted-random test, Circular Self-test Path(CSTP), self-feedback test

中图分类号: 

• TP302