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计算机工程 ›› 2011, Vol. 37 ›› Issue (13): 13-16. doi: 10.3969/j.issn.1000-3428.2011.13.004

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可进化芯片的FPGA接口设计与实现

段 欣1,陈利光1,王 健1,来金梅1,鲍丽春2   

  1. (1. 复旦大学专用集成电路与系统国家重点实验室,上海 201203;2. 北京航天飞控中心,北京100094)
  • 收稿日期:2010-12-10 出版日期:2011-07-05 发布日期:2011-07-05
  • 作者简介:段 欣(1983-),男,硕士研究生,主研方向:集成电路;陈利光、王 健,讲师;来金梅,教授;鲍丽春,工程师
  • 基金资助:

    国家“863”计划基金资助项目(2007AA01Z285);上海市科技创新行动计划基金资助项目(08706200101)

Design and Implementation of FPGA Interface for Evolvable Chip

DUAN Xin  1, CHEN Li-guang   1, WANG Jian  1, LAI Jin-mei  1, BAO Li-chun  2   

  1. Design and Implementation of FPGA Interface for Evolvable Chip
  • Received:2010-12-10 Online:2011-07-05 Published:2011-07-05

摘要:

针对FPGA IP核在可进化可编程系统芯片(SoPC)中嵌入时存在FPGA IP核端口时序控制和位流下载的问题,实现一种适用于可进化SoPC芯片的FPGA接口。该FPGA接口使用异步FIFO、双口RAM的结构和可扩展的读/写命令传输方式来实现FPGA IP核与系统的异步通信。嵌入式CPU可以通过FPGA接口实现FPGA IP核的片内位流配置。FPGA接口中的硬件随机数发生器实现进化算法的硬件加速。使用自动验证平台与FPGA原型验证平台对FPGA接口进行验证来实现验证的收敛。测试结果表明,FPGA接口成功实现了嵌入式CPU与FPGA IP核的通信,完成芯片内的进化。

关键词: 可编程系统芯片, FPGA接口, 硬件加速器, 验证平台

Abstract:

This paper proposes the design and implementation of a System on Programmable Chip(SoPC) interface to solve the problems of timing control and bit stream downloading of embedded Field Programmable Gate Array(FPGA) IP core in the evolvable SoPC. The FPGA interface uses asynchronous FIFO and dual port RAM structure, scalable read/write command transmission to achieve asynchronous communication between FPGA IP core and the system. Embedded CPU achieves the on-chip bit stream configuration of FPGA IP core via FPGA interface. Hardware random number generator in the FPGA interface is used to accelerate the evolutionary algorithm. Automatic verification platform and FPGA prototyping platform are used for the verification of FPGA interface to achieve convergence of verification. Test results show that FPGA interface implements the communication between embedded CPU and FPGA IP core successfully, completes on-chip evolution.

Key words: System on Programmable Chip(SoPC), Field Programmable Gate Array(FPGA) interface, hardware accelerator, verification platform

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