摘要:
为提高可扩展处理器体系结构(SPARC)的设计抽象层次和仿真速度,设计一种符合第8版SPARC(SPARC V8)的事务级模型。该模型基于TLM2.0标准,采用解释型指令集仿真方法实现程序执行。通过构建验证环境,证明该事务级模型能够正确运行并跟踪SPARC V8程序,仿真速度比寄存器传输级提高2个数量级。
关键词:
可扩展处理器体系结构,
事务级模型,
指令集仿真,
仿真速度,
寄存器传输级
Abstract:
In order to raise the level of design abstraction and simulation speed of Scalable Processor Architecture(SPARC) processor, a SPARC V8 processor Transaction Level Model(TLM) is designed in this paper. This model is based on TLM2.0 standard and interpretive instruction set simulation technology. Results of the test show that the model can execute and trace SPARC V8 programs exactly and the simulation speed of it is improved two orders of magnitude than Register Transfer Level(RTL) design.
Key words:
Scalable Processor Architecture(SPARC),
Transaction Level Model(TLM),
instruction set simulation,
simulation speed,
Register Transfer Level(RTL)
中图分类号:
周海洋, 葛宁, 于立新, 李玉红. 基于TLM2.0的SPARC事务级建模[J]. 计算机工程, 2011, 37(14): 248-250.
ZHOU Hai-Xiang, GE Ning, XU Li-Xin, LI Yu-Gong. Transaction Level Modeling of SPARC Based on TLM2.0[J]. Computer Engineering, 2011, 37(14): 248-250.