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计算机工程 ›› 2011, Vol. 37 ›› Issue (14): 248-250. doi: 10.3969/j.issn.1000-3428.2011.14.084

• 工程应用技术与实现 • 上一篇    下一篇

基于TLM2.0的SPARC事务级建模

周海洋 1,2,葛 宁 1,于立新 2,李玉红 2   

  1. (1. 清华大学电子工程系,北京 100084;2. 北京微电子技术研究所,北京 100076)
  • 收稿日期:2011-01-17 出版日期:2011-07-20 发布日期:2011-07-20
  • 作者简介:周海洋(1981-),男,工程师、硕士,主研方向:微处理器仿真,嵌入式系统设计;葛 宁,教授、博士;于立新,研究员;李玉红,工程师、硕士

Transaction Level Modeling of SPARC Based on TLM2.0

ZHOU Hai-yang 1,2, GE Ning 1, YU Li-xin 2, LI Yu-hong 2   

  1. (1. Department of Electronic Engineering, Tsinghua University, Beijing 100084, China; 2. Beijing Microelectronics Technology Institute, Beijing 100076, China)
  • Received:2011-01-17 Online:2011-07-20 Published:2011-07-20

摘要:

为提高可扩展处理器体系结构(SPARC)的设计抽象层次和仿真速度,设计一种符合第8版SPARC(SPARC V8)的事务级模型。该模型基于TLM2.0标准,采用解释型指令集仿真方法实现程序执行。通过构建验证环境,证明该事务级模型能够正确运行并跟踪SPARC V8程序,仿真速度比寄存器传输级提高2个数量级。

关键词: 可扩展处理器体系结构, 事务级模型, 指令集仿真, 仿真速度, 寄存器传输级

Abstract:

In order to raise the level of design abstraction and simulation speed of Scalable Processor Architecture(SPARC) processor, a SPARC V8 processor Transaction Level Model(TLM) is designed in this paper. This model is based on TLM2.0 standard and interpretive instruction set simulation technology. Results of the test show that the model can execute and trace SPARC V8 programs exactly and the simulation speed of it is improved two orders of magnitude than Register Transfer Level(RTL) design.

Key words: Scalable Processor Architecture(SPARC), Transaction Level Model(TLM), instruction set simulation, simulation speed, Register Transfer Level(RTL)

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